Âåðñèÿ äëÿ ïå÷àòè

TIA: LSim áèáëèîòåêà äëÿ ñèìóëÿöèè ïðîöåñîâ

Äàòà: 2017-03-28

Äîáàâëåíî: komatic

Òåìà: SCL



lsim



LSim áèáëèîòåêà äëÿ ñèìóëÿöèè îáúåêòîâ óïðàâëåíèÿ
ìíîãî èíòåðåñíûõ îòêðûòûõ áëîêîâ
ìîæåò áûòü èñïîëüçîâàíà äëÿ îïòèìèçàöèè ïàðàìåòðîâ èëè äëÿ äåìîíñòðàöèè/òåñòèðîâàíèÿ ðàáîòû ñèñòåì óïðàâëåíèÿ.





FB_„LSim_PT1‛
Ýëåìåíò PT1 ïðîïîðöèîíàëüíîé ïåðåäà÷è ñ çàäåðæêîé ïåðâîãî ïîðÿäêà ìîæåò áûòü èñïîëüçîâàí äëÿ ñèìóëÿöèè òåìïåðàòóðíûõ ñèñòåì



lsim







FB „LSim_PT1asym‛
Ýëåìåíò PT1 â êîòîðîì ðåàêöèÿ ðàçëè÷íà â çàâèñèìîñòè îò ïîçèòèâíîãî èëè íåãàòèâíîãî âîçäåéñòâèÿ. èñïîëüçîâàíèå - ñèìóëÿöèÿ òåìïåðàòóðíîé ñèñòåìû ñ ðàçëè÷íûì ïîâåäåíèåì ïðè íàãðåâå è îõëàæäåíèè.



lsim







FB „LSim_PT2osc‛
Ýëåìåíò PT2 ñèìóëèðóþùèõ êîëåáàòåëüíóþ ñèñòåìó, ìîæåò èñïîëüçîâàòüñÿ äëÿ ñèìóëÿöèè ìåõàíè÷åñêèõ ñèñòåì, êîòîðûå ñîâåðøàþò óäàð/ïîâîðîò è êîëåáëþòñÿ. Ïðåêðàñíî ïîäõîäèò äëÿ áàçîâîé íàñòðîéêè áûñòðûõ ðåãóëÿòîðîâ.



lsim







FB „LSim_PT2aper‛
Ýëåìåíò PT2 áåç ïåðåðåãóëèðîâàíèÿ, ìîæíî èñïîëüçîâàòü êàê ñèìóëÿöèþ spring pendulum (òàêîé ñëîæíûé ìàÿòíèê).



lsim







FB „LSim_PT3‛
Ýëåìåíò çàäåðæêè òðåòüåé ñòåïåíè, ñîäåðæèò òðè ïîñëåäîâàòåëüíûõ PT1 ýëåìåíòà, ìîæåò ñèìóëèðîâàòü òåìåðòóðíóþ ñèñòåìó ñ íåñêîëüêèìè ýëåìåíòàìè õðàíèåíèÿ. source



lsim







FB „LSim_PDT1‛
Ñèìóëèðóåò ïîâåäåíèå PDT1 ýëåìåíòà (ïðîèçâîäíàÿ ïåðâîãî ïîðÿäêà)



lsim







FB „LSim_I‛
Ñèìóëèðóåò ïðîñòóþ èíòåãðàëüíóþ ñèñòåìó, ìîæåò áûòü èñïîëüçîâàí, íàïðèìåð, êàê ñèìóëÿöèÿ íàïîëíåíèÿ åìêîñòè.



lsim







FB „LSim_IT1‛
Ñèìóëèðóåò èíòåãðàòîð ñ çàäåðæêîé, ìîæíî èñïîëüçîâàòü äëÿ ñèìóëÿöèè êëàïàíà ñ ñåðâîìîòîðîì.



lsim







FB „LSim_TempProcess‛
Ñèìóëèðóåò àñèìåòðè÷íûé òåìïåðàòóðíûé ïðîöåñ êîòîðûé ìîæåò áûòü àêòèâíî íàãðåâàòüñÿ è îõëàæäàòüñÿ (àêòèâíî èëè ïàñèâíî)









FB „LSim_Lagging‛
Ñèìóëèðóåò ýëåìåíò çàäåðæêè, ìîæíî ïðèìåíèòü íàïðèìåð äëÿ ñèìóëÿöèè êîíâååðíûõ ñèñòåì.



lsim







FB „ LSim_DT1‛
Ñèìóëèðóåò ýëåìåíò ïðîèçâîäíîé ñ çàäåðæêîé



lsim







FB „LSim_AllPass1OrdReal‛
Ñèìóëèðóåò ïðîõîæäåíèå ïåðâîãî ïîðÿäêà ñ íóëÿìè



lsim







FB „LSim_AllPass2OrdReal‛
Ñèóëèðóåò ïðîõîæäåíèå âòîðîãî ïîðÿäêà ñ íóëÿìè



lsim







FB „LSim_PT3HeatCool‛
Ñèìóëèðóåò òåìïåðàòóðíóþ ñèñòåìó PT3, ñ îòäåëüíûì óïðàâëåíèåì äëÿ íàãðåâà è îõëàæäåíèÿ









LSim_PT1





FUNCTION_BLOCK "LSim_PT1"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 1.0;   // time constant T1 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0)
      status : Word;   // status (if #tmLag1 <= 0 then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRf1 : Real;
      statRe1 : Real;
      statOverfirst : Bool;
      statOutput : Real;
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a PT1-System
    //
    //              gain
    //  F(p) = ---------------
    //          tmLag1 * p + 1
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1 <= 0 THEN
      #error := TRUE;
      #status := W#16#8001;     // Parameter Error
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    IF #calcParam = True OR NOT #statOverfirst THEN
      #statOverfirst:=1;
    // Z-parameters For Laplace PT1-System
    #statRe1 := - EXP(-#cycle/#tmLag1);
    #statRf1 := #gain*(1 + #statRe1);
    END_IF;
   
    // Differencial Equation of PT1-System
    #statOutput := #input*#statRf1 - #statOutput*#statRe1;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    IF #reset THEN
      #statOutput := 0;
    END_IF;
   
    #output := #statOutput;
END_FUNCTION_BLOCK

LSim_PT1asym





FUNCTION_BLOCK "LSim_PT1asym"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1up : Real := 1.0;   // time constant T1 [sec] rising input
      tmLag1down : Real := 10.0;   // time constant T1 [sec] falling input
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0 or #tmLag2 <= 0)
      status : Word;   // status (if #error = TRUE then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRf1up : Real;   // Z-parameter 1 (rising xn)
      statRe1up : Real;   // Z-parameter 2 (rising xn)
      statRf1dn : Real;   // Z-parameter 1 (falling xn)
      statRe1dn : Real;   // Z-parameter 2 (falling xn)
      statRf1 : Real;   // active Z-parameter 1
      statRe1 : Real;   // active Z-parameter 2
      statOverfirst : Bool;
      statOutput : Real;
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a PT1-System with two different Time-Constants
    //
    //  tmLag1up: Time-Constant for positive Inputsignal changes
    //  tmLag1down: Time-Constant for negative Inputsignal changes
    // 
    //                gain
    //  Fup(p) = ----------------
    //           tmLag1up * p + 1
    //         
    //                    gain
    //  Fdown(p) = ------------------
    //             tmLag1down * p + 1
    //         
    //  Call the simulation in a cyclic interrupt with
    //  //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1up <= 0 OR #tmLag1down <= 0 THEN
      #error := TRUE;
      #status := W#16#8001;     // Parameter Error
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    IF #calcParam = True OR NOT #statOverfirst THEN
      #statOverfirst:=1;
    // Z-parameters for Laplace PT1-System (rising signal change)
    #statRe1up := - EXP(-#cycle/#tmLag1up);
    #statRf1up := #gain*(1 + #statRe1up);
    // Z-parameters for Laplace PT1-System (falling signal change)
    #statRe1dn := - EXP(-#cycle/#tmLag1down);
    #statRf1dn := #gain*(1 + #statRe1dn);
    END_IF;
   
    // save delayed output signals
    #statRyn1:= #statOutput;
   
    // Change the parameter sets, dependent to Input Change
    IF (#input - #statRxn1) > 0 THEN
      #statRf1 := #statRf1up;
      #statRe1 := #statRe1up;
    ELSIF (#input - #statRxn1) < 0 THEN
       #statRf1 := #statRf1dn;
       #statRe1 := #statRe1dn;
    ELSE
      ;
    END_IF;
   
    // Differencial Equation of PT1-System
    #statOutput := #input*#statRf1 - #statRyn1*#statRe1;
   
    // save delayed input signals
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    IF #reset THEN
      #statOutput := 0;
    END_IF;
   
    #output := #statOutput;
     
     
   
   
END_FUNCTION_BLOCK

LSim_PT2osc





FUNCTION_BLOCK "LSim_PT2osc"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      omega : Real := 2.0;   // angular frequency of the undampened vibrations [1/sec]
      damp : Real := 0.2;   // damping (0 < D < 1)
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (0 >= damp >= 1 or #omega <= 0)
      status : Word;   // status (if #error = TRUE then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn2 : Real;   // delayed input signal (n-2)
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn2 : Real;   // delayed output signal (n-2)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRb1 : Real;
      statRb2 : Real;
      statRa1 : Real;
      statRa2 : Real;
      statRo : Real;
      statSigma : Real;
      statNue : Real;
      statOverfirst : Bool;
      statOutput : Real;
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a vibrating PT2-System
    //
    //                  gain
    //  F(p) = ----------------------------------
    //         SQR(p/omega) + 2*damp*p/omega + 1
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #damp >= 1 OR #damp <= 0 OR #omega <= 0 THEN
      #error := TRUE;
      #status := W#16#8001;
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True THEN
    // Calculate z-parameters for oscillating PT2-System
    #statRo := EXP(-2*#omega*#damp*#cycle);
    #statSigma := (COS(#omega * #cycle * SQRT(1 - SQR(#damp)))) * EXP(-#damp*#omega*#cycle);
    #statNue := (SIN(#omega*#cycle*SQRT(1-SQR(#damp)))) * (EXP(-#damp*#omega*#cycle)) * (#damp / SQRT(1 - SQR(#damp)));
    #statRa1 := -2*#statSigma;
    #statRa2 := #statRo;
    #statRb1 := #gain*(1 - #statSigma - #statNue);
    #statRb2 := #gain*(#statRo - #statSigma + #statNue);
    END_IF;
   
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput:=0;
      #error := False;
      #status := W#16#0000;
    END_IF;
   
    // save delayed output signals
    #statRyn2:=#statRyn1;
    #statRyn1:= #statOutput;
   
    // difference equatation for PT2-System
    #statOutput := #statRxn1* #statRb1 + #statRxn2*#statRb2 - #statRyn1*#statRa1 - #statRyn2*#statRa2;
   
    // save delayed input signals
    #statRxn2 := #statRxn1;
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
END_FUNCTION_BLOCK

LSim_PT2aper





FUNCTION_BLOCK "LSim_PT2aper"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 2.0;   // time constant T1 [sec]
      tmLag2 : Real := 0.2;   // time constant T2 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0 or #tmLag2 <= 0 or #tmLag1 = #tmLag2)
      status : Word;   // status (if #error = TRUE then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn2 : Real;   // delayed input signal (n-2)
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn2 : Real;   // delayed output signal (n-2)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRf1 : Real;
      statRf2 : Real;
      statRe1 : Real;
      statRe2 : Real;
      statAlpha : Real;
      statBeta : Real;
      statGamma : Real;
      statDelta : Real;
      statOverfirst : Bool;
      statOutput : Real;   // Output signal
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a aperiodic PT2-System
    // 
    //                    gain
    //  F(p) = -----------------------------
    //         (tmLag1*p + 1)*(tmLag2*p + 1)
    //        
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1 <= 0 OR #tmLag2 <= 0 OR #tmLag1 = #tmLag2 THEN
      #error := TRUE;
      #status := W#16#8001;     // Parameter Error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True OR NOT #statOverfirst THEN
      #statOverfirst := 1;
      // Calculate z-parameters for IT1-System
      #statAlpha := EXP(- #cycle / #tmLag1);
      #statBeta := EXP(- #cycle / #tmLag2);
      #statGamma := #tmLag1 / (#tmLag1 - #tmLag2);
      #statDelta := #tmLag2 / (#tmLag1 - #tmLag2);
      #statRe1 := - #statAlpha - #statBeta;
      #statRe2 := #statAlpha * #statBeta;
      #statRf1 := #gain * (1 - #statGamma * #statAlpha + #statDelta * #statBeta);
      #statRf2 := #gain * (#statAlpha * #statBeta - #statGamma * #statBeta + #statAlpha * #statDelta);
    END_IF;
   
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput := 0;
    END_IF;
    //save delayed input signals
    #statRxn2 := #statRxn1;
    #statRxn1 := #input;
   
    //save delayed output signals
    #statRyn2:=#statRyn1;
    #statRyn1:= #statOutput;
   
    // difference equatation of the PT2-System
    #statOutput := #statRxn1* #statRf1 + #statRxn2*#statRf2 - #statRyn1*#statRe1 - #statRyn2*#statRe2;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
END_FUNCTION_BLOCK

LSim_PT3





FUNCTION_BLOCK "LSim_PT3"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      input : Real;   // input variable
      tmLag1 : Real := 29.0;   // time lag 1 in s
      tmLag2 : Real := 17.5;   // time lag 2 in s
      tmLag3 : Real := 3.1;   // time lag 3 in s
      gain : Real := 1.0;   // proportional gain
      disturb : Real;   // disturbance variable (additional to "input")
      cycle : Real := 0.1;   // sample time [in sec]
      reset : Bool;   // complete restart (#output = #input)
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0 or #tmLag2 <= 0 or #tmLag3 <= 0)
      status : Word;   // status (if #error = TRUE then status = 16#8001)
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statFback1 : Real;   // feedback path value 1
      statFback2 : Real;   // feedback path value 2
      statFback3 : Real;   // feedback path value 3
   END_VAR
 
   VAR_TEMP
      tempHvar : Real;   // help variable
      tempCycleR : Real;   // cycle to real
      tempTmLag1R : Real;   // time lag 1 to real
      tempTmLag2R : Real;   // time lag 2 to real
      tempTmLag3R : Real;   // time lag 3 to real
      tempOutvNew : Real;   // new output variable
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of an PT3-system
    //
    //                               gain
    //  F(p) = ------------------------------------------------------
    //         (tmLag1 * p + 1) * (tmLag2 * p + 1) * (tmLag3 * p + 1)
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1 <= 0 OR #tmLag2 <= 0 OR #tmLag3 <= 0 THEN
      #error := TRUE;
      #status := W#16#8001;     // Parameter Error
      #output := #input; //write output data
      #statFback1 := #input; //write static data
      #statFback2 := #input;
      #statFback3 := #input;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    IF #reset THEN //complete restart routine
     
      #output := #input;//write output data
      #statFback1 := #input;//write static data
      #statFback2 := #input;
      #statFback3 := #input;
   
    ELSE //cycle mode routine
     
      #tempCycleR  := #cycle*1000; //transform data type
      #tempTmLag1R := #tmLag1*1000;
      #tempTmLag2R := #tmLag2*1000;
      #tempTmLag3R := #tmLag3*1000;
     
      IF #tempCycleR * 0.5 > #tempTmLag1R THEN //limit TM_LAG1
        #tempTmLag1R := #tempCycleR * 0.5;
      END_IF;
     
      IF #tempCycleR * 0.5 > #tempTmLag2R THEN //limit TM_LAG2
        #tempTmLag2R := #tempCycleR * 0.5;
      END_IF;
     
      IF #tempCycleR * 0.5 > #tempTmLag3R THEN //limit TM_LAG2
        #tempTmLag3R := #tempCycleR * 0.5;
      END_IF;
     
      //1. first order lag algorithm
      #tempHvar     := #tempCycleR / (#tempTmLag1R * 2.0);
      #tempHvar     := (#gain * (#input + #disturb) - #statFback1) * #tempHvar / (#tempHvar + 1.0);
      #tempOutvNew  := #tempHvar + #statFback1;
      #statFback1  := #tempHvar * 2.0 + #statFback1;
     
      //2. first order lag algorithm
      #tempHvar     := #tempCycleR / (#tempTmLag2R * 2.0);
      #tempHvar     := ((#tempOutvNew - #statFback2) * #tempHvar) / (#tempHvar + 1.0);
      #tempOutvNew  := #tempHvar + #statFback2;
      #statFback2  := #tempHvar * 2.0 + #statFback2;
     
      //3. first order lag algorithm
      #tempHvar     := #tempCycleR / (#tempTmLag3R * 2.0);
      #tempHvar     := ((#tempOutvNew - #statFback3) * #tempHvar) / (#tempHvar + 1.0);
      #tempOutvNew  := #tempHvar + #statFback3;
      #statFback3  := #tempHvar * 2.0 + #statFback3;
     
      #output := #tempOutvNew; //write output
     
    END_IF;
   
   
   
END_FUNCTION_BLOCK

LSim_PDT1





FUNCTION_BLOCK "LSim_PDT1"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 2.0;   // time constant T1 [sec]
      tmLag2 : Real := 0.2;   // time constant T2 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0 or #tmLag2 <= 0)
      status : Word;   // status (if #error = TRUE then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn2 : Real;   // delayed input signal (n-2)
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn2 : Real;   // delayed output signal (n-2)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRb1 : Real;
      statRb0 : Real;
      statRa1 : Real;
      statOverfirst : Bool;
      statOutput : Real;
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of an PD-T1 System
    //
    //         gain * (1 + tmLag2*p)
    //  F(p) = ------------------------------
    //            (1 + tmLag1*p)
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1 <= 0 OR #tmLag2 <= 0 THEN
      #error := True;
      #status := W#16#8001;     // Parameter Error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True OR NOT #statOverfirst THEN
      #statOverfirst := 1;
    // Calculate z-parameters for oscilating PT2-System
    #statRa1 := -EXP(-#cycle/#tmLag1);
    #statRb0 := #gain *(#tmLag2/#tmLag1);
    #statRb1 := #gain *(1 + #statRa1 - (#tmLag2/#tmLag1));
    END_IF;
   
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput:=0;
      #error := False;
      #status := W#16#0000;
    END_IF;
   
    // save delayed output-signals
    #statRyn1:= #statOutput;
   
    // difference equatation for PT2-system
    #statOutput := #input * #statRb0 +  #statRxn1* #statRb1 - #statRyn1*#statRa1;
   
    // save delayed input-signals
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
END_FUNCTION_BLOCK

LSim_I





FUNCTION_BLOCK "LSim_I"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 1.0;   // time constant T1 [sec]
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0)
      status : Word;   // status (if #tmLag1 <= 0 then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRa1 : Real;
      statRb1 : Real;
      statOverfirst : Bool;
      statOutput : Real;   // output signal
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a I-System
    //
    //             1
    //  F(p) = -----------
    //         (tmLag1*p)
    //          
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1 <= 0 THEN
      #error := True;
      #status := W#16#8001;     // Parameter Error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True OR NOT #statOverfirst THEN
    #statOverfirst:=1;
      // Calculate z-parameters for IT1-System
    #statRb1 := #cycle/#tmLag1;
    #statRa1 := -1;
   
    END_IF;
   
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statOutput:=0;
    END_IF;
   
    // save delayed output-signals
    #statRyn1:= #statOutput;
   
    // difference equatation for the I-system
    #statOutput := #statRxn1* #statRb1 - #statRyn1*#statRa1;
   
    // save delayed input-signals
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
   
END_FUNCTION_BLOCK

LSim_IT1





FUNCTION_BLOCK "LSim_IT1"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 5.0;   // time constant T1 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0)
      status : Word;   // status (if #tmLag1 <= 0 then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn2 : Real;   // delayed input signal (n-2)
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn2 : Real;   // delayed output signal (n-2)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRf1 : Real;
      statRf2 : Real;
      statRe1 : Real;
      statRe2 : Real;
      statAlpha : Real;
      statOverfirst : Bool;
      statOutput : Real;   // output signal
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a IT1-System
    // 
    //               gain
    //  F(p) = ------------------
    //         p * (tmLag1*p + 1)
    //        
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check parameter
    IF #tmLag1 <= 0 THEN
      #error := True;
      #status := W#16#8001;     // Parameter Error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True OR NOT #statOverfirst THEN
      #statOverfirst:=1;
    // calculates the z-parameter for the difference equatation of the IT1-System
    #statAlpha := EXP(-#cycle/#tmLag1);
    #statRe1 := -1 - #statAlpha;
    #statRe2 := #statAlpha;
    #statRf1 := #gain*(#cycle +(#statAlpha - 1)*#tmLag1);
    #statRf2 := #gain*(-#statAlpha*#cycle+(1-#statAlpha)*#tmLag1);
    END_IF;
   
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput:=0;
    END_IF;
   
    // save delayed output-signals
    #statRyn2:=#statRyn1;
    #statRyn1:= #statOutput;
   
    // difference equatation for IT1-System
    #statOutput := #statRxn1* #statRf1 + #statRxn2*#statRf2 - #statRyn1*#statRe1 - #statRyn2*#statRe2;
   
    // save delayed input-signals
    #statRxn2 := #statRxn1;
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
    #statOutput := #maxOut;
    #maxReached := True;
    ELSE
      #maxReached := False;
    END_IF;
    
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
   
END_FUNCTION_BLOCK

LSim_TempProcess





FUNCTION_BLOCK "LSim_TempProcess"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      inTemp : Real;   // Temperature Input [K] ("useHeatPow" must be FALSE to use this input)
      useHeatPow : Bool := TRUE;   // Use "heatPow" as input
      activHeatPow : Bool;   // Turn on heating ("useHeatPow" must be TRUE to use this input)
      activCoolRth : Bool;   // Turn on cooling by "statRThCool"
      activCoolPow : Bool;   // Turn on cooling by "coolPow"
      coolPow : Real;   // Positive value of energy reduction caused by succeding process [W]
      ambTemp : Real := 20.0;   // Ambient Temperature in °C
      cycle : Real := 0.1;   // Call cycle time in s
      reset : Bool;   // Reset internal variables
   END_VAR
 
   VAR_OUTPUT
      outTemp : Real;   // [°C]
      interTemp : Real;   // [°C]
   END_VAR
 
   VAR_IN_OUT
      heatPow : Real;   // Heater Energy in [W]
   END_VAR
 
   VAR
      statRthTrans1 : Real := 1.5;   // Input thermal resistance in transition to capacitor 1 [K/W]
      statRth1 : Real := 1.0;   // Thermal resistance parallel to thermal capacity 1 [K/W]
      statRthTrans2 : Real := 1.5;   // Thermal resistance for energy transition from capacity 1 to capacity 2 [K/W]
      statRth2 : Real := 1.0;   // Thermal resistance parallel to thermal capacity 2 [K/W]
      statRthCool : Real := 2.0;   // Thermal resistance of cooling device [K/W]
      statCth1 : Real := 10.0;   // Thermal Capacity 1 [Ws/K]
      statCth2 : Real := 30.0;   // Thermal Capacity 2 [Ws/K]
      statZInt1 : Real;   // internal
      statZInt2 : Real;   // internal
      statUc1 : Real;   // internal
      statUc2 : Real;   // internal
      statIth2 : Real;   // internal
   END_VAR
 
   VAR_TEMP
      tempSumPoint1 : Real;
      tempSumPoint2 : Real;
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulates of an asymmetrical temperature process which can be
    //actively heated and cooled down (also passively).
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    IF #reset = TRUE THEN
      // Reset all variables
      #statUc1 := 0;
      #statUc2 := 0;
      #statIth2 := 0;
      #tempSumPoint1 := 0;
      #tempSumPoint2 := 0;
      #statZInt1 := 0;
      #statZInt2 := 0;
    END_IF;
   
    IF #useHeatPow = FALSE THEN
      // Temperature Input will be used, so "heatPow" will be used as output
      #heatPow := ((#inTemp - #ambTemp - #statUc1) / #statRthTrans1);
    END_IF;
   
    // Calculate fist summing point
    IF (#activHeatPow = TRUE) OR (#useHeatPow = FALSE) THEN
      #tempSumPoint1 := #heatPow - (#statUc1 / #statRth1) - #statIth2;
    ELSE
      #tempSumPoint1 := 0 - (#statUc1 / #statRth1) - #statIth2;
    END_IF;
   
    // Calculate integrator 1
    #statUc1 := #statUc1 + (((#tempSumPoint1 / #statCth1) + #statZInt1) * #cycle * 0.5);
    #statZInt1 := #tempSumPoint1 / #statCth1;
   
    // Calculate intermidiate temperature
    #interTemp := #statUc1 + #ambTemp;
   
    // Calculate thermal power flow from Integrator 1 to Integrator 2
    #statIth2 := ((#statUc1 - #statUc2) / #statRthTrans2);
   
    // Calculate summing point 2
    IF #activCoolPow = TRUE THEN
      #tempSumPoint2 := #statIth2 - (#statUc2 / #statRth2) - #coolPow;
    ELSE
      #tempSumPoint2 := #statIth2 - (#statUc2 / #statRth2);
    END_IF;
   
    IF #activCoolRth = TRUE THEN
      // Cooling is activated
      #tempSumPoint2 := #tempSumPoint2 - (#statUc2 / #statRthCool);
    END_IF;
   
    // Calculate Integrator 2
    #statUc2 := (#cycle * 0.5 * ((#tempSumPoint2 / #statCth2) + #statZInt2)) + #statUc2;
    #statZInt2 := #tempSumPoint2 / #statCth2;
   
    // Calculate Output Temperature
    #outTemp := #statUc2 + #ambTemp;
   
END_FUNCTION_BLOCK

LSim_Lagging





FUNCTION_BLOCK "LSim_Lagging"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.01
   VAR_INPUT
      input : Real;
   END_VAR
 
   VAR_OUTPUT
      output : Real;
   END_VAR
 
   VAR_IN_OUT
      delayCycles : UInt;
   END_VAR
 
   VAR
      statDelayStore : Array[0..#MAX] of Real;
      statIndexRead : Int;
      statIndexWrite : Int;
   END_VAR
 
   VAR CONSTANT
      MAX : Int := 100;
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2017 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8 / S7-1200 FW V4.1
    //Engineering:   STEP 7 Prof. V13 SP1 Upd9 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed for S7-1500
    //Functionality: Simulation of an Tt-System (Lagging)
    //
    //  F(p) = EXP(-p * delayCycles * cyclic interrupt time)
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //02.00.01 02.03.2017 Siemens Industry Online Support Optimize program code
    //=============================================================================
   
    // Check Parameters
    IF #delayCycles > #MAX THEN
      #delayCycles := INT_TO_UINT(#MAX);
    ELSE
      #delayCycles := #delayCycles;
    END_IF;
   
    IF #statIndexWrite < #delayCycles THEN
      #statDelayStore[#statIndexWrite] := #input;   // write input at delayStore indexWrite
      #statIndexRead := #statIndexWrite + 1;
      #output := #statDelayStore[#statIndexRead];   // read output from delayStore indexWrite + 1
      #statIndexWrite := #statIndexWrite + 1;       // increment delayStore indexWrite
    ELSE // maximum reached
      #statDelayStore[#statIndexWrite] := #input;   // write input at delayStore maximum
      #statIndexRead := 0;                          // set indexRead to beginning
      #output := #statDelayStore[#statIndexRead];   // read output from delayStore indexRead
      #statIndexWrite := 0;                         // set indexWrite to beginning
    END_IF;
   
   
END_FUNCTION_BLOCK

LSim_DT1





FUNCTION_BLOCK "LSim_DT1"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 2.0;   // time constant T1 [sec]
      tmLag2 : Real := 0.5;   // time constant T2 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real := -100.0;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0)
      status : Word;   // status (if #tmLag1 <= 0 then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRb0 : Real;
      statRa1 : Real;
      statOverfirst : Bool;
      statOutput : Real;   // output signal
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of a DT1-System
    //
    //         gain * tmLag2 * p
    //  F(p) = ------------------------------
    //            (1 + tmLag1*p)
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check of the parameter
    IF #tmLag1 <= 0 THEN
      #error := true;
      #status := W#16#8001; // parameter error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True OR NOT #statOverfirst THEN
      // Calculate the z-parameter for the DT1-System
      #statOverfirst := 1;
      #statRa1 := -EXP(-#cycle/#tmLag1);
      #statRb0 := #gain*(#tmLag2/#tmLag1);
    END_IF;
   
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statOutput:=0;
      #error := false;
      #status := W#16#0000;
    END_IF;
   
    // save delayed output-signals
    #statRyn1:= #statOutput;
   
    //  difference equatation for DT1-system
    #statOutput := #input * #statRb0 - #statRxn1* #statRb0 - #statRyn1*#statRa1;
   
    // save delayed input-signals
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached := True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
   
END_FUNCTION_BLOCK

LSim_AllPass1OrdReal





FUNCTION_BLOCK "LSim_AllPass1OrdReal"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 2.0;   // time constant T1 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0)
      status : Word;   // status (if #tmLag1 <= 0 then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRb1 : Real;
      statRa1 : Real;
      statOutput : Real;   // output signal
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of an All-Pass 1. Order with real p-Poles
    //
    //         gain * (1 - tmLag1*p)
    //  F(p) = ---------------------
    //            (1 + tmLag1*p)
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check of the parameter
    IF #tmLag1 <= 0 THEN
      #error := True;
      #status := W#16#8001;     // Parameter Error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
   
    // Z-parameters
    IF #calcParam = True THEN
    // Calculate z-parameters for allpass filter
       #statRa1 := -EXP(-#cycle/#tmLag1);
       #statRb1 := #gain*(2 + #statRa1);
   
    END_IF;
    // reset Memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statOutput:=0;
      #error := False;
      #status := W#16#0000;
    END_IF;
   
    // save delayed output signal
    #statRyn1:= #statOutput;
   
    // Differencial Equation of all-pass filter 1. order
    #statOutput := #input * (-#gain) +  #statRxn1* #statRb1 - #statRyn1*#statRa1;
   
    // save delayed input signals
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
END_FUNCTION_BLOCK

LSim_AllPass2OrdReal





FUNCTION_BLOCK "LSim_AllPass2OrdReal"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      calcParam : Bool;   // recalculate with new parameters
      input : Real;   // input signal
      tmLag1 : Real := 2.0;   // time constant T1 [sec]
      tmLag2 : Real := 0.2;   // time constant T2 [sec]
      gain : Real := 1.0;   // gain factor
      cycle : Real := 0.1;   // cyclic time [sec]
      maxOut : Real := 100.0;   // max. output limit
      minOut : Real;   // min. output limit
      reset : Bool;   // resets all relevant parameters to ‘0’ including the output
   END_VAR
 
   VAR_OUTPUT
      error : Bool;   // error (#tmLag1 <= 0 or #tmLag2 <= 0 or #tmLag2 = #tmLag1)
      status : Word;   // status (if #error = TRUE then status = 16#8001)
      maxReached : Bool;   // output has reached max. limit
      minReached : Bool;   // output has reached min. limit
      output : Real;   // output signal (if #error = FALSE)
   END_VAR
 
   VAR
      statRxn2 : Real;   // delayed input signal (n-2)
      statRxn1 : Real;   // delayed input signal (n-1)
      statRyn2 : Real;   // delayed output signal (n-2)
      statRyn1 : Real;   // delayed output signal (n-1)
      statRb1 : Real;
      statRb2 : Real;
      statRa1 : Real;
      statRa2 : Real;
      statRe1 : Real;
      statRe2 : Real;
      statRk1 : Real;
      statOverfirst : Bool;
      statOutput : Real;   // output signal
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of an All-Pass 2. Order with real p-Poles
    //
    //         gain * (1 - tmLag1*p) * (1 - tmLag2*p)
    //  F(p) = --------------------------------------
    //            (1 + tmLag1*p) * (1 + tmLag2*p)
    //         
    //  Call the simulation in a cyclic interrupt with
    //  cyclic interrupt time at least = tmLag1/10!
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    // check of the parameter
    IF #tmLag1 <= 0 OR #tmLag2 <= 0 OR #tmLag1 = #tmLag2 THEN
      #error := TRUE;
      #status := W#16#8001;     // Parameter Error
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput := 0;
      #output := 0;
      RETURN;
    ELSE
      #error := FALSE;
      #status := W#16#0000;     // no error
    END_IF;
   
    // calculates the z-parameter for the difference equatation
    IF #calcParam = True OR NOT #statOverfirst THEN
    // Calculate z-parameters for oscilating PT2-System
    #statOverfirst:=1;
    #statRe1 := -EXP(-#cycle/#tmLag1);
    #statRe2 := -EXP(-#cycle/#tmLag2);
    #statRk1 := (2* (#tmLag2 + #tmLag1))/(#tmLag2 - #tmLag1);
    #statRa1 := #statRe1 + #statRe2;
    #statRa2 := #statRe1*#statRe2;
    #statRb1 := #gain*(#statRa1+ #statRk1*(#statRe2 - #statRe1));
    #statRb2 := #gain*(#statRa2 -#statRk1*(#statRe2 - #statRe1));
    END_IF;
   
    // reset memory
    IF #reset = True THEN
      #statRxn1 := 0.0;
      #statRyn1 := 0.0;
      #statRxn2 := 0.0;
      #statRyn2 := 0.0;
      #statOutput:=0;
      #error := False;
      #status := W#16#0000;
    END_IF;
   
    // save delayed output-signals
    #statRyn2:=#statRyn1;
    #statRyn1:= #statOutput;
   
    // difference equatation for PT2-system
    #statOutput := #input * #gain +  #statRxn1* #statRb1 + #statRxn2*#statRb2 - #statRyn1*#statRa1 - #statRyn2*#statRa2;
   
    // save delayed input-signals
    #statRxn2 := #statRxn1;
    #statRxn1 := #input;
   
    // max limit of acutating variable
    IF #statOutput > #maxOut THEN
      #statOutput := #maxOut;
      #maxReached:= True;
    ELSE
      #maxReached := False;
    END_IF;
   
    // min limit of acutating variable
    IF #statOutput < #minOut THEN
      #statOutput := #minOut;
      #minReached := True;
    ELSE
      #minReached := False;
    END_IF;
   
    #output := #statOutput;
   
END_FUNCTION_BLOCK
 

LSim_PT3HeatCool





FUNCTION_BLOCK "LSim_PT3HeatCool"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 2.0
   VAR_INPUT
      inputHeat : Real;   // input variable heating
      inputCool : Real;   // input variable cooling
      disturbHeat : Real;   // disturbance variable heating (additional to "inputHeat")
      disturbCool : Real;   // disturbance variable cooling (additional to "inputCool")
      ambTemp : Real := 20.0;   // ambient temperature
      gainHeat : Real := 1.5;   // proportional gain heating
      gainCool : Real := 3.0;   // proportional gain cooling
      tmLag1Heat : Real := 60.0;   // time lag 1 heating [s]
      tmLag2Heat : Real := 10.0;   // time lag 2 heating [s]
      tmLag3Heat : Real;   // time lag 3 heating [s]
      tmLag1Cool : Real := 60.0;   // time lag 1 cooling [s]
      tmLag2Cool : Real := 10.0;   // time lag 2 cooling [s]
      tmLag3Cool : Real;   // time lag 3 cooling [s]
      cycle : Real := 0.1;   // sample time [s]
   END_VAR
 
   VAR_OUTPUT
      output : Real;   // output variable
   END_VAR
 
   VAR_IN_OUT
      reset : Bool;   // complete restart
   END_VAR
 
   VAR
      statFback1 : Array[0..1] of Real;   // feedback value 1 heating/cooling
      statFback2 : Array[0..1] of Real;   // feedback value 2 heating/cooling
      statFback3 : Array[0..1] of Real;   // feedback value 3 heating/cooling
   END_VAR
 
   VAR_TEMP
      tempHvar : Real;   // helper
      tempCycleR : Real;   // sampling time
      tempTmLag1R : Real;   // delay time 1
      tempTmLag2R : Real;   // delay time 2
      tempTmLag3R : Real;   // delay time 3
      tempIndex : Int;   // control variable
      tempOutvNew : Array[0..1] of Real;   // new output value heating/cooling
   END_VAR
 
 
BEGIN
    //=============================================================================
    //SIEMENS AG
    //(c)Copyright 2016 All Rights Reserved
    //-----------------------------------------------------------------------------
    //Library:       Library for Controlled System Simulation
    //Tested with:   S7-1500 FW V1.8
    //Engineering:   STEP 7 Prof. V13 SP1 Upd6 (TIA Portal)
    //Restrictions:  Cyclic interrupt
    //Requirements:  memory card needed
    //Functionality: Simulation of an PT3-system with heating and cooling input
    //-----------------------------------------------------------------------------
    //Change log table:
    //Version  Date       Expert in charge                Changes applied
    //02.00.00 03.02.2016 Siemens Industry Online Support Release (STEP 7 V13 SP1)
    //=============================================================================
   
    #tempOutvNew[0] := (#inputHeat + #disturbHeat) * #gainHeat;
    #tempOutvNew[1] := (#inputCool + #disturbCool) * #gainCool;
   
    IF #reset
    THEN
      //restart
     
      //write output parameters
      #output := #tempOutvNew[0] - #tempOutvNew[1] + #ambTemp;
     
      //write static local variables
      FOR #tempIndex := 0 TO 1 DO
        #statFback1[#tempIndex] := #tempOutvNew[#tempIndex];
        #statFback2[#tempIndex] := #statFback1[#tempIndex];
        #statFback3[#tempIndex] := #statFback2[#tempIndex];
      END_FOR;
     
      #reset := FALSE;
    ELSE
      //smoothing 
      #tempCycleR := #cycle;
      IF #tempCycleR < 0.001
      THEN
        //low limit sampling time
        #tempCycleR := 0.001;
      END_IF;
     
      FOR #tempIndex := 0 TO 1 DO
       
        IF #tempIndex = 0
        THEN
          #tempTmLag1R := #tmLag1Heat;
          #tempTmLag2R := #tmLag2Heat;
          #tempTmLag3R := #tmLag3Heat;
        ELSE
          #tempTmLag1R := #tmLag1Cool;
          #tempTmLag2R := #tmLag2Cool;
          #tempTmLag3R := #tmLag3Cool;
        END_IF;
       
        //1.delay
        IF #tempTmLag1R >= #tempCycleR * 0.5
        THEN
          #tempHvar := #tempCycleR / (2.0 * #tempTmLag1R + #tempCycleR);
          #tempHvar := (#tempOutvNew[#tempIndex] - #statFback1[#tempIndex]) * #tempHvar;
          //calculate new output value
          #tempOutvNew[#tempIndex] := #statFback1[#tempIndex] + #tempHvar;
          //calculate new feedback value
          #statFback1[#tempIndex] := #statFback1[#tempIndex] + 2.0 * #tempHvar;
        ELSE  //----------------------------------- implicit PT1
          #tempHvar := #tempCycleR / (#tempTmLag1R + #tempCycleR);
          //calculate new feedback value
          #statFback1[#tempIndex] := #statFback1[#tempIndex] + (#tempOutvNew[#tempIndex] - #statFback1[#tempIndex]) * #tempHvar;
          //calculate new output value
          #tempOutvNew[#tempIndex] := #statFback1[#tempIndex];
        END_IF;
       
        //2.delay heating
        IF #tempTmLag2R >= #tempCycleR * 0.5
        THEN
          #tempHvar := #tempCycleR / (2.0 * #tempTmLag2R + #tempCycleR);
          #tempHvar := (#tempOutvNew[#tempIndex] - #statFback2[#tempIndex]) * #tempHvar;
          //calculate new output value
          #tempOutvNew[#tempIndex] := #statFback2[#tempIndex] + #tempHvar;
          //calculate new feedback value
          #statFback2[#tempIndex] := #statFback2[#tempIndex] + 2.0 * #tempHvar;
        ELSE
          #statFback2[#tempIndex] := #tempOutvNew[#tempIndex];
        END_IF;
       
        //3.delay heating
        IF #tempTmLag3R >= #tempCycleR * 0.5
        THEN
          #tempHvar := #tempCycleR / (2.0 * #tempTmLag3R + #tempCycleR);
          #tempHvar := (#tempOutvNew[#tempIndex] - #statFback3[#tempIndex]) * #tempHvar;
          //calculate new output value
          #tempOutvNew[#tempIndex] := #statFback3[#tempIndex] + #tempHvar;
          //calculate new feedback value
          #statFback3[#tempIndex] := #statFback3[#tempIndex] + 2.0 * #tempHvar;
        ELSE
          #statFback3[#tempIndex] := #tempOutvNew[#tempIndex];
        END_IF;
       
      END_FOR;
     
      #output := #tempOutvNew[0] - #tempOutvNew[1] + #ambTemp;
    END_IF;
END_FUNCTION_BLOCK



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